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BUILT-IN SELF-TEST SYSTEM FOR VLSI CIRCUIT CHIPS

机译:用于VLSI电路芯片的内置自测系统

摘要

A system (10) self-control logic incorporated in a circuit board (12) large scale integrated (LSI) for performing dynamic tests of the operation of the main logic function (14) comprises a control register (32) containing a series of static latches (150) connected to the serial transfer of control data and for generating control signals of the control system. A shift register input (36) connected to the control register (32) for performing serial transfer of control data and to the main logic function (14) for performing the parallel transfer of control data is formed a series arrangement of static scales. An output register (38) connected to the input register (36) for performing serial transfer of control data and to the main logic function (14) for performing the parallel transfer of control data is formed of a series arrangement of static scales (182). An enable signal and control synchronization is locked by a latch (78) and validation control and synchronization triggered by a system timing signal for generating timing signals of the input and output registers. A control strobe signal is blocked by a control sampling flip-flop (76) and sampled by a latch (80) and serves as a validation signal of the control register. The sampling hold signal and the control signal blocked validation and synchronization control are triggered by the system timing signal and serve as a control register of the synchronization signal. A multiplexer (40) output the control data decodes a selection signal generated by the control command register and provides thus represented control data to a spindle (60) for controlling data output.
机译:包含在电路板(12)大规模集成(LSI)中的用于执行对主逻辑功能(14)的操作的动态测试的系统(10)自控逻辑,包括控制寄存器(32),该控制寄存器包含一系列静态锁存器(150)连接到控制数据的串行传输并用于产生控制系统的控制信号。连接到用于执行控制数据的串行传送的控制寄存器(32)和用于执行控制数据的并行传送的主逻辑功能(14)的移位寄存器输入(36)形成一系列的静态标尺。连接到用于执行控制数据的串行传送的输入寄存器(36)和用于执行控制数据的并行传送的主逻辑功能(14)的输出寄存器(38)由一系列的静态标尺(182)形成。 。使能信号和控制同步由锁存器(78)锁定,并且验证控制和同步由系统定时信号触发,用于生成输入和输出寄存器的定时信号。控制选通信号被控制采样触发器(76)阻挡并且被锁存器(80)采样,并且用作控制寄存器的确认信号。采样保持信号和控制信号被阻止的验证和同步控制由系统定时信号触发,并用作同步信号的控制寄存器。输出控制数据的多路复用器(40)对由控制命令寄存器产生的选择信号进行解码,并将由此表示的控制数据提供给主轴(60),用于控制数据输出。

著录项

  • 公开/公告号EP0245463A1

    专利类型

  • 公开/公告日1987-11-19

    原文格式PDF

  • 申请/专利权人 ETA SYSTEMS INC.;

    申请/专利号EP19860907130

  • 发明设计人 BACH RANDALL E.;RESNICK DAVID R.;

    申请日1986-11-07

  • 分类号G01R31/28;

  • 国家 EP

  • 入库时间 2022-08-22 06:56:12

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