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BUILT-IN SELF-TEST SYSTEM FOR VLSI CIRCUIT CHIPS.

机译:用于VLSI电路芯片的内置自测系统。

摘要

a system (10) is included in a control logic circuit (12) for wafer scale integrated (lsi) to test the operation of the dynamic logic function key (14) includes a controller (32) comprising a series of static scales (150) connected to the transfer data and to generate control signals to controlin the control system. an input register (36) connected to the shift register (32) to control the transfer of control and data set to the main logic function (14) to transfer data in parallel to control consists of a series of automatic layout static.an output register (38) connected to the input register (36) to carry out the transfer control data set and the main logic function (14) to transfer data in parallel to control consists of a series of combination static scales (182) ).a validation signal and synchronization control is blocked by a scale (78) for validation and synchronization control and triggered by a timing signal from the system to generate timing signals of input and output registers.a sampling control signal is blocked by a scale of sampling control (76), and sampled by a switching signal (80), and is used as a validation of the control register.the signal blocking signal sampling control and block validation and synchronization control are activated by the timing signal from the system and serve as a timing signal from the controller.a multiplexer (40) decodes a data output control signal generated by the selection of the control register provides control and monitoring data represented with a pin (60) for output control.
机译:系统(10)包括在用于晶片级集成(lsi)的测试逻辑电路的控制逻辑电路(12)中,以测试动态逻辑功能键(14)的操作,该系统包括控制器(32),该控制器(32)包括一系列静态秤(150)连接到传输数据并生成控制信号以控制控制系统。连接到移位寄存器(32)的输入寄存器(36),用于控制控制权的传递和设置到主逻辑功能(14)的数据,以并行地传递数据以进行控制,包括一系列自动布局静态变量。 (38)连接到输入寄存器(36)以执行传输控制数据集,主逻辑功能(14)并行传输数据以进行控制,它由一系列组合静态标尺(182)组成。同步控制被用于验证和同步控制的标度(78)阻止,并由来自系统的定时信号触发以生成输入和输出寄存器的定时信号。采样控制信号被标度控制(76)阻止,并由开关信号(80)进行采样,并用作控制寄存器的验证。信号阻塞信号的采样控制以及块验证和同步控制由来自系统的定时信号激活。多路复用器(40)对通过选择控制寄存器而产生的数据输出控制信号进行解码,以提供用引脚(60)表示的控制和监视数据以进行输出控制。

著录项

  • 公开/公告号EP0245463A4

    专利类型

  • 公开/公告日1989-05-26

    原文格式PDF

  • 申请/专利权人 ETA SYSTEMS INC.;

    申请/专利号EP19860907130

  • 发明设计人 BACH RANDALL E.;RESNICK DAVID R.;

    申请日1986-11-07

  • 分类号G01R31/28;

  • 国家 EP

  • 入库时间 2022-08-22 06:34:44

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