Protective triac without gate realized with the aid of a high-resistance substrate

摘要

1. Trigger-electrode protection triac with avalanche firing constituted by a semiconductor wafer incorporating two antiparallel-connected thyristors (TH1, TH2), each thyristor having an anode zone (AN1, AN2) of type P, a central zone (CE1, CE2) of type N, a trigger zone (GA1, GA2) of type P and a cathode zone (CA1, CA2) of type N, the central zones of type N of the two thyristors being formed by the same substrate layer of type N, a metallization (ME1, ME2) covering each face of the wafer, the anode zone and the cathode zone lying at said face, and short-circuiting holes (CC1, CC2) through which the trigger zone of type P extends through the cathode zone of type N up to the metallization covering the latter, characterized in that the central region comprises a weak concentration of type N so that the superficial inverse breakdown voltage at the level of the junction between the central zone and the trigger zone is higher than the trigger voltage of the triac and that for each thyristor (TS1, TS2) at least one specific zone (AS1, AS2) of type N is provided which is doped more than the central zone and separates the central zone from the trigger zone, said zone being arranged in alignment with a portion of the trigger zone of the corresponding thyristor but not extending through to the periphery of the semiconductor wafer.