Multiple input digital video features processor for TV signals

摘要

A video features processor for use with a display device includes a first clock that is line locked to the display and a skew- shifted second clock that is phase locked to the horizontal sync component of an auxiliary video signal. An A/D converter, responsive to the skew-shifted clock, develops digital samples representative of the auxiliary video signal. A clock transfer circuit, responsive to the line- locked and skew- shifted clocks, translates digital samples occurring synchronously with the skew-shifted clock signal to digital samples occurring synchronously with the line-locked clock signal. The digital samples occurring synchronously with the line-locked clock signal are stored in a memory.