Digital video features processor for TV signals

摘要

A video features processor for use with a display device includes a first clock (FCS) that is line locked to the display (HSS_D) and a skew-shifted second clock (SCS) that is phase locked to the horizontal sync component (HSS_s) of an auxiliary video signal (Y_s, U_s, V_s). An A/D converter (122), responsive to the skew-shifted clock, develops digital samples representative of the auxiliary video signal. A clock transfer circuit (124), responsive to the line-locked and skew-shifted clocks, translates digital samples occurring synchronously with the skew-shifted clock signal to digital samples occurring synchronously with the line-locked clock signal. The digital samples occurring synchronously with the line-locked clock signal are stored in a memory (150).