Digital adaptive filter for a high throughput digital adaptive processor

摘要

The weights of least mean square (LMS) adaptive filter are updated with a different set of taps than are used to form the output of the adaptive filter in the adaptive processing device of the present invention. As a result of performing the multiplications and sums required for the filter operation simultaneously, an integral number of clock cycle delays appear in the narrowband and error feedback channels. The number of taps of the tapped delay line of the invention are increased, whereby the increased delay through the delay line may be used to compensate for a delay through the filter of an integral number of clock delay cycles. Instantaneous weight updating in accordance with the signal being utilized, may then be achieved at a clock rate frequency that is ten times or more greater than prior art adaptive filters.