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A dynamic random access memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor
A dynamic random access memory device having a single-crystal transistor on a trench capacitor structure and a fabrication method therefor
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机译:在沟槽电容器结构上具有单晶晶体管的动态随机存取存储装置及其制造方法
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摘要
Dynamic random access memory (DRAM) devices are described wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor. A fabrication method for such devices is also described wherein crystallisation seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO₂/Si₃N₄/SiO₂ is provided for the capacitor storage insulator. A thin layer of SiO₂ is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO₂ layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.
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机译:描述了动态随机存取存储器(DRAM)设备,其中在单晶半导体芯片上形成了包括存取晶体管和存储电容器的各个单元,并且更具体地,描述了三维动态随机存取存储器(DRAM)设备结构具有堆叠在沟槽电容器顶部的单晶访问晶体管。还描述了用于这种器件的制造方法,其中,通过围绕单元的单晶半导体区域和/或从沟槽的垂直侧壁提供结晶种子,并且其中,通过绝缘体隔离访问晶体管。在该结构中,沟槽位于包含重掺杂的N +多晶硅的p +型衬底中。提供SiO 2 / Si 3 N 4 / SiO 2复合膜作为电容器存储绝缘体。 SiO 2薄层设置在多晶硅上。轻掺杂的p型外延硅层位于衬底和SiO 2层上方。用于存储单元的访问晶体管位于沟槽电容器的顶部。 N +掺杂的材料将晶体管的源极区域连接到沟槽内的多晶硅。万一沿沟槽表面有大量泄漏电流,可以在沟槽表面的顶部提供中等掺杂的p区。
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