Highly parallel computer architecture employing crossbar switch with selectable pipeline delay

摘要

A crossbar switch (4) in a highly parallel com­puter architecture for interconnecting any one of a plu­rality of arithmetic units (2) to any one of a plurality of memories (6) comprising :a multiplexer section for pivoting switching of signal paths between said arithmetic units (2) and said memories ; anda control section for controlling said signal path switching to allocate selected signal paths in accordance with an algorithm under execution, said control section comprising control circuitry for creating pipeline delay of steering vectors which specify the memory to be read from and pipeline delay of data returning from the memory.