首页> 外国专利> METHOD OF FORMING LOW-RESISTANCE CONTACTS TO PREOHMIC REGIONS IN VERY LARGE SCALE INTEGRATED DEVICES

METHOD OF FORMING LOW-RESISTANCE CONTACTS TO PREOHMIC REGIONS IN VERY LARGE SCALE INTEGRATED DEVICES

机译:在大型集成设备中形成与低氧区域的低电阻接触的方法

摘要

A method of forming low-resistive contact to at least two preohmic regions formed in a silicon substrate having a thick insulating layer thereon, including the steps of depositing a polysilicon on the insulating layer, performing an anisotropic etch for opening the preohmic regions, sputter-depositing a titanium deposit, the deposited titanium having electrical disconnections on the vertical side-walls of the opening regions, siliciding the titanium deposit, and depositing a metal silicide deposit for preventing electrical disconnections. Another embodiment uses a sputter-deposited titanium silicide deposit instead of titanium silicide. Still another embodiment includes the step of forming holes by an anisotropic etch, depositing polysilicon in the holes and on the insulating layer, sputter-depositing an titanium deposit, forming an titanium silicide deposit, and depositing a metal silicide deposit.
机译:一种形成至少两个在其上具有厚绝缘层的硅衬底中形成的预欧姆区的低电阻接触的方法,该方法包括以下步骤:在绝缘层上沉积多晶硅;执行各向异性蚀刻以打开预欧姆区;溅射-沉积钛沉积物,沉积的钛在开口区域的垂直侧壁上具有电断开,硅化钛沉积物,并沉积金属硅化物沉积物以防止电断开。另一个实施方案使用溅射沉积的硅化钛沉积物代替硅化钛。又一实施例包括以下步骤:通过各向异性蚀刻形成孔,在孔中和绝缘层上沉积多晶硅,溅射沉积钛沉积物,形成硅化钛沉积物,以及沉积金属硅化物沉积物。

著录项

  • 公开/公告号GB8921421D0

    专利类型

  • 公开/公告日1989-11-08

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS COMPANY LIMITED;

    申请/专利号GB19890021421

  • 发明设计人

    申请日1989-09-22

  • 分类号H01L27/04;H01L21/28;H01L21/285;H01L21/3205;H01L21/768;H01L21/822;H01L23/532;

  • 国家 GB

  • 入库时间 2022-08-22 06:28:56

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