Data processing system having interfacing circuits assigned to a common I/O port address by utilizing a specific bit line of a common bus

摘要

An interface circuit can assign a common input/output port address to a plurality of I/O circuits. Each common I/O port is defined in terms of pages. In an actual data input/output, a specific port address is used for port control so as to select one common page. The interface circuit has a first decoder for decoding a specific port address signal. The interface circuit also had a data setter for setting data supplied from a specific bit line of the data bus. The data is set in the data setter in accordance with the decoded signal from the first decoder. Each of the plurality of I/O circuits has a second decoder for decoding the common I/O port address signal. An output from the setter enables a corresponding one of second decoders. As a result, a specific page is selected. When an interrupt request signal is supplied from any one of the I/O circuits, NAND gates generate a specific bit signal for a specific bit line of the data bus in response to the decoded signal from the first decoder so as to allow the system to determine which page is generating the interrupt request signal. The system checks the bit position of the data origin, thereby detecting the page which has supplied the interrupt request signal to the system.