Method for simulating an open fault in a logic circuit comprising field effect transistors and simulation models for implementing the method

摘要

A method for simulating an open fault in a logic circuit comprising field effect transistors utilizes a simulation model which is employed and which takes the fault condition signal storage into consideration by way of an output stage. Given the appearance of a fault- influence signal at the output of a simulation stage, this maintains the through- connection of the signal which appeared immediately before the influenced signal to the simulation model output. In order to take reloading events in the real logic circuit into consideration, this through-connection is canceled after a prescribable time interval.