AMORPHOUS SILICON THIN FILM TRANSISTOR ARRAY OF TOP STAGGER TYPE

摘要

PURPOSE:To improve the yield of the device by sharply reducing a broken source wiring upon etching by forming over the entirety of the upper portion of the source wiring an amorphous silicon layer more wider than the source wiring or an amorphous silicon layer and a silicon nitride layer disposed on the former. CONSTITUTION:A plurality of gate electrodes 1 are connected to each other through an Al gate wiring 4. A plurality of source electrodes 2 composed of ITOs are connected to each other through a source wiring 5. An amorphous silicon layer 6 and a silicon nitride layer 7 are formed on an FET section, and formed on the entire upper portion of the source wiring 5 wider than the source wiring 5. Hereby, the source wiring 5 is covered with another amorphous silicon layer 6 of the gate insulating layer 9 and with the silicon nitride 7. Accordingly, there is produced no pin hole and the like at the same portion in the above three layers. When the gate wiring 4 is etched and so on, the source wiring 5 is not damaged, and hence any trouble of broken source wiring 5 is greatly reduced.