CARRY PROPAGATING CIRCUIT FOR PARALLEL FULL ADDER

摘要

PURPOSE:To attain the arithmetic processing at a high speed by making a carry signal communicating circuit on a main channel at a lower order digit side just viewed from the termination of a bypass into an off condition when the bypass becomes an on condition and communicating only a signal to pass through the bypass to an upper order digit side. CONSTITUTION:When bypasses #1', #2'... become the on condition, a carry signal communicating circuit 1 on main channels #1, #2... at the lower order digit side just viewed from the termination of the bypass is controlled to an off condition, and therefore, the competition of the signal via the bypasses #1', #2'... and the signal to propagate the main channels #1, #2,... in a ripple way can be evaded. Thus, since it is not necessary to use a multi-input combining circuit such as a NAND gate, NOR gate, etc., in a carry signal communicating channel 1, the time necessary to the carry propagation can be shortened only for the signal propagation delay of the gate itself.