BUS COMPETITION SYSTEM

摘要

PURPOSE:To omit a specific controller and to optionally specify the position of a slot by dividing a bus to be a competing object into plural blocks and forming an intra-block bus competition signal line and an inter-block bus competition signal line. CONSTITUTION:When bus competition is competed with either one of other devices on the preceding slots of the self-device, the output of an OR gate 16 is turned to 'H' if any one of bus request signals ABRQ to CBRQ, ARQ to CRQ is outputted from the devices of the preceding slots even when a flip flop (FF) 12 is set up (Q='H') and a bus request is generated, so that an FF 19 is not set up in the succeeding clock, i.e. the FF 12 is not reset, and the bus request of the self-device is waited. When the bus request of the preceding slot device is disconnected and a bus using state is set up, all the bus request signals ABRQ to CBRQ, ARQ to CRQ of other devices are turned to 'H' and the bus is enabled to be used in the succeeding clock.