PURPOSE:To shorten the queuing time of a central processing unit by providing a main storage device with an instruction decoding circuit, predicting a free space in the main storage by a specific instruction, generating a check address by using the free space, and starting the collation timing of the duplicated main storage device. CONSTITUTION:The 1st and 2nd main storage devices 20, 21 are respectively constituted of memory blocks 210, 211, instruction decoding circuits 220, 221, address generating means, and discrepancy detecting means 250, 251. The circuits 220, 221 decode specific instructions in order to guarantee the coincidence of written data. The address generating means decode the specific instructions to forecast the existence of accesses, generate check addresses and send check address requests to the other system. The means 250, 251 detect the coincidence of data between the self-system and the other system by using the check addresses. Thus, the queuing time of the central processing unit can be shortened.
展开▼
