Digital multiplier architecture with triple array summation of partial products

摘要

The invention performs the multiplication and/or accumulation of digital numbers in either two's complement or unsigned magnitude representation. A modified Booth algorithm minimizes the number of partial products generated. Two adder arrays sum the partial products in parallel to generate intermediate values which are then summed by a third adder array. The partial products are divided between the two adder arrays in a manner which optimizes the speed of the circuit.