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Digital multiplier architecture with triple array summation of partial products
Digital multiplier architecture with triple array summation of partial products
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机译:具有部分乘积的三重数组求和的数字乘法器体系结构
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摘要
The invention performs the multiplication and/or accumulation of digital numbers in either two's complement or unsigned magnitude representation. A modified Booth algorithm minimizes the number of partial products generated. Two adder arrays sum the partial products in parallel to generate intermediate values which are then summed by a third adder array. The partial products are divided between the two adder arrays in a manner which optimizes the speed of the circuit.
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