METHOD AND DEVICE FOR SELECTIVELY POSTING WRITING CYCLES USING AN ANTEMEMORY CONTROL UNIT 82385

摘要

A microcomputer system using a CPU 80386 and a cache controller 82385, can operate with dynamic bus sizing (where the CPU operates in interaction with devices which may or may not be 32 bit wide) and also ensure posted entries. Unfortunately, these two characteristics present a possibility of incompatibility if a write cycle is posted to a device which cannot transfer 32 bits during a single cycle. The present invention provides logic which eliminates this incompatibility. An address decoder makes it possible to decode the label part of a claimed address on a local bus CPU in order to determine whether the claimed address is inside or outside of an address range which defines devices. with possibility of cache memory. Any cache-capable device is by definition 32-bit wide, and posted writes are therefore only allowed to cache-capable devices. Consequently, the microcomputer system using the invention posts write cycles to devices with cache memory possibility. Write cycles to devices without the possibility of cache cannot be posted.