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Phase locked loop with optimally controlled bandwidth

机译:具有最佳控制带宽的锁相环

摘要

A phase locked loop has a digital phase comparator, a filter with multiple bandwidths, a voltage controlled oscillator and a frequency divider connected to the phase comparator to complete the loop. Control circuitry is coupled to both the phase comparator and filter for controlling switching between a wide bandwidth and a narrow bandwidth. The switching in bandwidth is in response to either detecting when the output signal is within a predetermined range of the reference frequency for a predetermined time period or detecting when the output signal exceeds and falls below the reference frequency a predetermined number of times. The control circuit is implemented with circuitry which accurately detects either condition and is capable of blocking any premature change of bandwidth.
机译:锁相环具有一个数字相位比较器,一个具有多个带宽的滤波器,一个压控振荡器和一个与该相位比较器相连的分频器,以完成环路。控制电路耦合到相位比较器和滤波器两者,以控制宽带宽和窄带宽之间的切换。带宽的切换是响应于检测到输出信号何时处于参考频率的预定范围内达预定时间段,或者响应于检测到输出信号何时超过或低于参考频率达预定次数。该控制电路由能够精确检测任一条件并能够阻止带宽的任何过早变化的电路实现。

著录项

  • 公开/公告号US4920320A

    专利类型

  • 公开/公告日1990-04-24

    原文格式PDF

  • 申请/专利权人 MOTOROLA INC.;

    申请/专利号US19880285997

  • 发明设计人 LLOYD P. MATTHEWS;

    申请日1988-12-19

  • 分类号H03K17/00;H03L7/00;

  • 国家 US

  • 入库时间 2022-08-22 06:07:36

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