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Loop bandwidth adjusting method for phase locked-loop unit and associated loop bandwidth adjusting unit and phase recovery module

机译:锁相环单元的环路带宽调整方法以及相关的环路带宽调整单元和相位恢复模块

摘要

A bandwidth adjusting method for a phase-locked loop (PLL) unit of a phase recovery module includes: adjusting an operating bandwidth of the PLL unit to a first bandwidth; measuring multiple first phase errors between a compensated input signal, which is generated according to an input signal and a phase compensating signal that the PLL unit generates, and a reference clock signal, and obtaining a first statistical value of the first phase errors; adjusting the operating bandwidth of the PLL unit to a second bandwidth; measuring multiple second phase differences between the compensated input signal and the reference clock signal, and obtaining a second statistical value of the second phase differences; and adjusting the operating bandwidth according to the first statistical value and the second statistical value. The first bandwidth and the second bandwidth are obtained by interpolating an upper bandwidth limit and a lower bandwidth limit.
机译:一种用于相位恢复模块的锁相环单元的带宽调整方法,包括:将所述PLL单元的工作带宽调整为第一带宽;测量根据输入信号和PLL单元产生的相位补偿信号产生的补偿输入信号与参考时钟信号之间的多个第一相位误差,得到第一相位误差的第一统计值;将PLL单元的工作带宽调整为第二带宽;测量补偿后的输入信号与参考时钟信号之间的多个第二相位差,并获得第二相位差的第二统计值;根据第一统计值和第二统计值调整工作带宽。通过内插带宽上限和带宽下限来获得第一带宽和第二带宽。

著录项

  • 公开/公告号US10075285B2

    专利类型

  • 公开/公告日2018-09-11

    原文格式PDF

  • 申请/专利权人 MSTAR SEMICONDUCTOR INC.;

    申请/专利号US201715610743

  • 发明设计人 TING-NAN CHO;KAI-WEN CHENG;TAI-LAI TUNG;

    申请日2017-06-01

  • 分类号H04L7;H04L7/033;

  • 国家 US

  • 入库时间 2022-08-21 13:06:15

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