PURPOSE:To perform a rounding processing at a high speed by providing a means to each mantissa part of a multiplicand and a multiplier detecting the bit length having continuous 0 from the lowest-order together with an adding means for bit length having two continuous 0, and a bit length comparing means. CONSTITUTION:The additions 10 and 11 of reading bits and the detections 12 and 13 of bit length having continuous 0 from the lowest-order bit of a multiplicand and a multiplier respectively are carried out to the mantissa part which sets and outputs the multiplicand and the multiplier to the reading registers 3 and 4 from a floating point register 2. A multiplier 14 obtains the product of a mantissa part to set it to an intermediate product register 16 and then sets the bit length having continuous 0 to a register 17 via an adder 15. A comparator 18 estimates the OR of all bits lower than the rounding bit of the product as 1 when the sum of the bit lengths having 0 continuous from each lowest-order bit of the multiplicand and the multiplier is equal to the bit length having 0 continuous from the lowest-order bit of the product and at the same time smaller than the bit length lower in order than the rounding bit of the product. Otherwise the comparator 18 predicts the OR as 0. Thus the rounding processing speed is increased and the predicted OR is written into the register 2. Then the multiplication of floating decimal-points is ended.
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