SURFACE FIELD EFFECT TRANSISTOR HAVING LOWERED SOURCE AND/OR DRAN AREA FOR SUPER LARG-SCALE DEVICE

摘要

PURPOSE: To provide a surface field effect transistor which can be completely realized in an ULSI manufacturing process and in which the occurrence of current doubling phenomena in a drain junction can be reduced by making the surface level of a semiconductor substrate in a drain area lower than that of the substrate in a channel area, overlapping an insulating gate layer and a gate electrode. CONSTITUTION: The MOSFET structure of a surface field effect transistor is realized, constituted of an insulating gate oxide layer 2, and the transistor contains a gate electrode 1 separated from a single-crystal silicon substrate 5 which also constitutes the channel area of the transistor and has first electric conductivity-type. The surface levels of the single-crystal silicon 5 in source and drain areas 3 on both surfaces of the gate electrode 1 are made lower than the surface level of the silicon in a channel area underneath the gate oxide 2 and gate electrode 1. Therefore, the transistor can be completely realized in the manufacturing process of an ultra-large scale integration(ULSI), and the occurrence of current amplification phenomena in the drain junction of the transistor can be reduced.