High speed CMOS comparator with hysteresis

摘要

A comparator circuit in accordance with the present invention includes a first stage (21, 27) which is a standard CMOS implementation of a differential amplifier. The differential outputs (3, 4) of the first stage are applied to the inputs of a second differential amplifier stage (32, 35) which is of the same design as the first stage. A hysteresis element (31) is added to the current mirror load (30, 34) of the second stage and is driven by an output (5) of the second stage. This second stage output (5) is applied to a threshold matching single-ended gain stage (40, 41). The output (7) of the gain stage (40, 41) is applied to a standard CMOS inverter (50, 51) which provides the final comparator output (8). The hysteresis element (31) is placed internally within the second stage (32, 35) to be driven by the second stage output (5) such that the voltage difference between the differential inputs (3, 4) to the second stage must exceed a preselected threshold voltage before the output (5) to the single-ended gain stage switches state.