HIGH SPEED CMOS COMPARATOR WITH HYSTERESIS

摘要

AbstractHIGH SPEED CMOS COMPARATOR WITH HYSTERESISA comparator circuit in accordance with thepresent invention includes a first stage which is astandard CMOS implementation of a differentialamplifier. The differential outputs of the firststage are applied to the inputs of a seconddifferential amplifier stage which is of the samedesign as the first stage. A hysteresis element isadded to the current mirror load of the second stageand is driven by an output of the second stage. Thissecond stage output is applied to a threshold matchingsingle-ended gain stage. The output of the gain stageis applied to a standard CMOS inverter which providesthe final comparator output. The hysteresis element isplaced internally within the second stage to be drivenby the second stage output such that the voltagedifference between the differential inputs to thesecond stage must exceed a preselected thresholdvoltage before the output to the single-ended gainstage switches state.