Structure of memory cell used for gallium arsenide SRAM (GaAs SRAM)

摘要

The memory cell structure comprises a cell latch having cell driving FET's (JD1,JD2) connected to load resistors (RL1,RL2), a pair of read bit lines for simultaneously reading the complementary data from the cell latch,a pair of write bit lines for simultaneously writing the complementary data in the cell latch, a plural read FET's (JR1,JR2) for transferring the complementary voltages (V1,V2) to the read bit lines and a plural write FET's (JW1,JW2) for transferring the complementary voltages of the write bit lines to the cell latch. The cell latch has only a data storing function, the red FET's (JR1,JW2) driving the bit line, thereby increasing the tolerance width of the threshold voltage variation.