Method of transmitting data at full bandwidth within a synchronous system when clock skew plus delay exceeds the cycle time

摘要

The invention expands the period of data stabilization between state devices to be 1.5 times the cycle time minus the clock skew. The invention requires that a clock signal (hereinafter "forwarded clock") be sent with data to the receiving subsystem. Such data is received by a capture latch, which is operated by special logic that receives the forwarded clock, and then proceeds to an ordinary state device in the receiving subsystem that is running synchronously with the receiving subsystem. This state device nominally captures the data 1.5 cycles after it was sent from a state device in the sending subsystem.