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Method for fabricating a self-aligned thin-film transistor utilizing planarization and back-side photoresist exposure

机译:利用平坦化和背面光刻胶曝光来制造自对准薄膜晶体管的方法

摘要

A method for fabricating self-aligned thin-film transistors (TFTs) includes the steps of: exposing a backside substrate surface, opposite to a principal substrate surface, to ultra-violet (UV) light to cause exposure of at least a photoresist layer portion which corresponds substantially to an area outside the shadow of a gate electrode formed on the principal substrate surface; developing the exposed photoresist portion to form a mask; etching a second insulation layer segment, using the mask, to form a remaining insulation layer segment, which is aligned with the gate electrode, and narrower than the gate electrode by a selected overlap distance, on each side thereof; and forming source and drain electrodes on a doped semiconductor layer which each overlap the gate electrode by the selected overlap distance. The overlap distance is a function of the UV exposure time, the photoresist development time and the etch time of the second insulation layer.
机译:一种自对准薄膜晶体管(TFT)的制造方法,包括以下步骤:将与主基板表面相对的背面基板表面暴露于紫外线(UV)中,以使至少光刻胶层部分曝光。基本上对应于在主基板表面上形成的栅电极的阴影之外的区域;显影曝光的光致抗蚀剂部分以形成掩模;使用掩模蚀刻第二绝缘层段,以在其每一侧上形成剩余的绝缘层段,该绝缘层段与栅电极对准并且比栅电极窄选定的重叠距离;在掺杂的半导体层上形成源电极和漏电极,所述源电极和漏电极各自以选定的重叠距离与栅电极重叠。重叠距离是UV曝光时间,光致抗蚀剂显影时间和第二绝缘层的蚀刻时间的函数。

著录项

  • 公开/公告号US5010027A

    专利类型

  • 公开/公告日1991-04-23

    原文格式PDF

  • 申请/专利权人 GENERAL ELECTRIC COMPANY;

    申请/专利号US19900499733

  • 发明设计人 GEORGE E. POSSIN;WEI CHING-YEU;

    申请日1990-03-21

  • 分类号H01L29/78;H01L21/00;

  • 国家 US

  • 入库时间 2022-08-22 05:46:37

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