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Reduced instruction set computer (RISC) type microprocessor executing instruction functions indicating data location for arithmetic operations and result location

机译:精简指令集计算机(RISC)型微处理器,执行指令功能,指示用于算术运算的数据位置和结果位置

摘要

A reduced instruction set type microprocessor which reduces loss of central processing unit (CPU) time. A circuit is provided to identify and keep track of whether an arithmetic instruction requires operands contained in internal registers or in main memory. First and second execution stage circuits are provided for executing the first and second instruction executing functions, respectively. The first execution stage circuit performs address calculation if the instruction involves main memory. The second execution stage circuit selects the appropriate operands and performs the arithmetic operation.
机译:减少指令集类型的微处理器,可减少中央处理器(CPU)时间的损失。提供了一种电路,用于识别并跟踪算术指令是否需要内部寄存器或主存储器中包含的操作数。提供第一和第二执行级电路,分别用于执行第一和第二指令执行功能。如果指令涉及主存储器,则第一执行级电路执行地址计算。第二执行级电路选择适当的操作数并执行算术运算。

著录项

  • 公开/公告号US5041968A

    专利类型

  • 公开/公告日1991-08-20

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号US19900535300

  • 发明设计人 YOSHIKO YAMAGUCHI;

    申请日1990-06-08

  • 分类号G06F9/38;G06F7/00;G06F13/00;

  • 国家 US

  • 入库时间 2022-08-22 05:46:04

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