REDUCED INSTRUCTION SET COMPUTER (RISC) TYPE MICROPROCESSOR

摘要

Abstract of the DisclosureA microprocessor for pipeline processing comprisesinstruction fetch stage means for fetching an instructionwhich has within itself a first instruction executingfunction and a second instruction executing function.First execution stage means are provided for executing thefirst instruction executing function of the instructionfrom the instruction fetch stage means, and also secondexecution stage means for executing the second instructionexecuting function of the instruction under pipelinecontrol following the completion of execution by the firstexecution stage means.