SHORT-SETUP TIME AND LOW-POWER CMOS BUS RECEIVER

摘要

PURPOSE: To minimize the pull up time of PFET and set up time of a latching circuit by so providing that a feedback means latches the signal output of an inverted input by a CMOS inverter and means for response to the latch output of the feed back means drives the latch signal to an output bus. CONSTITUTION: A complementary PFET(p-channel FET) of a CMOS (complementary metal-oxide semiconductor) inverter is replaced with a small CMOS inverter 202 or 206 and N(N-channel) FET 204 or 208, thus reducing the power consumption for improving the operating speed. This is based on the difference of the operational performance between the PFET and NFET. That is, the NFET is capable of changing the logical level at a higher speed than that of the PFET of the same size. These circuits also improve the set up time from high to low and vice versa for latching.