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INTEGRATED CIRCUIT STRUCTURE BODY PROVIDED WITH SELF-INSPECTION FUNCTION; SORTING METHOD OF GOOD INTEGRATED CIRCUIT CHIP BY USING IT

机译:具有自检功能的集成电路结构体;良品集成电路芯片的排序方法

摘要

PURPOSE:To surely judge, in a nondestructive manner, whether integrated circuit chips for an operating frequency which by far exceeds conventional operating frequencies such as Josephson integrated circuit chips or the like are good or not by a method wherein an integrated circuit under test and a test circuit are juxtaposed in different regions which are situated on the same board and which can be divided. CONSTITUTION:An integrated circuit 31 under test which is subjected to the judgment of whether it is good or not and a test circuit 32 which tests the integrated circuit 31 under test and which extracts a test data are juxtaposed in different regions 21, 22 which are situated on the same board 21 and which can be divided. Bonding pads 35 for test use which are required to connect the test circuit 32 to an external analysis apparatus are provided only in the region 22 which is situated on said board 20 and in which the test circuit 32 is formed. For example, a Josephson integrated circuit 31 under test is formed in a first region 21 of a board 20; a Josephson test circuit 32 which performs the operation test of the Josephson integrated circuit 31 under test and which extracts a test data is formed in a second region 22. The Josephson test circuit 32 is connected to the Josephson integrated circuit 31 under test by using interconnections 33 on the board 20.
机译:目的:以一种非破坏性的方式肯定地判断一种工作频率远远超过常规工作频率的集成电路芯片(例如约瑟夫森集成电路芯片等)是否良好,方法是通过一种被测集成电路和测试电路并排放置在同一块板上的不同区域中,这些区域可以划分。组成:一个被测集成电路31,被判断是否合格,一个测试电路32被并置在不同的区域21、22中,该测试电路32对被测集成电路31进行测试并提取测试数据。在同一块板21上可以分开。仅在位于所述板20上并且形成测试电路32的区域22中,提供了用于将测试电路32连接至外部分析设备所需的测试用的焊盘35。例如,被测试的约瑟夫森集成电路31形成在板20的第一区域21中;被测试的约瑟夫森集成电路31形成在板20的第一区域21中。在第二区域22中形成约瑟夫逊测试电路32,该约瑟夫逊测试电路32执行被测约瑟夫森集成电路31的操作测试并提取测试数据。约瑟夫森测试电路32通过互连与被测约瑟夫森集成电路31连接。板上的33个20。

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