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METHOD OF AND ARRAY FOR SEPARATING ADDRESS AREA OF A GROUP OF STORAGES IN DIGITAL SYSTEMS

机译:数字系统中一组存储区的地址划分方法和阵列

摘要

1. A method of realisation of a distributor of address space of memory groups in digital systems characterized in that the most significant part of address bus is compared, with the use of comparators sequence (K1/KN-1), with the lowest addresses of memory groups (P1/PN-1), and the results of such comparison are used to unblock the decoders (D0/DN-1) of memory groups (P0/PN-1) in such a manner that the zero decoder (D0) is unblocked when the most significant part of address bus is smaller than the most significant part of the lowest address of the first memory group (P1), the last decoder (DN-1) is unblocked when the most significant part of address bus is bigger than or equal to the most significant part of the lowest address of the last memory group (PN-1), and each of the remaining decoders (D1/DN-2) is unblocked when the most significant part of address bus is bigger than or equal to the most significant part of the lowest address of the memory group with the number compatible with the decoder's number, and lower than the most significant part of the lowest address of memory group with the further number.IMAGE
机译:1.一种在数字系统中实现存储器组的地址空间分配器的方法,其特征在于,使用比较器序列(K1 / KN-1)比较地址总线的最高有效部分,使用比较器序列的最低地址。存储组(P1 / PN-1),并且比较结果用于以零解码器(D0)解锁存储组(P0 / PN-1)的解码器(D0 / DN-1)当地址总线的最高有效部分小于第一个存储组(P1)的最低地址的最高有效部分时,解锁,最后一个解码器(DN-1)在地址总线的最高有效部分更大时,解锁等于或等于最后一个存储组的最低地址(PN-1)的最高有效部分,并且当地址总线的最高有效部分大于或时,其余的每个解码器(D1 / DN-2)都将不受阻塞等于内存组最低地址的最高有效部分,其编号与解码器的编号,并且比存储组的最低地址的最高有效部分低,并带有更多编号。

著录项

  • 公开/公告号PL158387B1

    专利类型

  • 公开/公告日1992-08-31

    原文格式PDF

  • 申请/专利权人

    申请/专利号PL19880272765

  • 发明设计人

    申请日1988-05-30

  • 分类号G06F12/02;

  • 国家 PL

  • 入库时间 2022-08-22 05:34:24

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