Circuit for storing availability states of logic resources such as memory cells, and for setting up addresses of free resources

摘要

The invention relates to the monitoring of the availability of logic resources, and particularly that of cells of a data memory of the RAM type, in which randomly received data are written. To do this, the invention provides a circuit for setting up the addresses of available data cells as a function of the free and occupied states of the data cells. The circuit comprises an array (1) of one-bit, at least write-addressable cells (2C, 2L) for storing availability-state bits for the data cells, and means (30 to 3J-1, 6L, 40 to 4I-1, 6C) connected to the outputs of all the cells of the array (100 to 1I-1J-1) for detecting those cells of the array each containing a free state bit ("1"). Preferably the address of a free data cell is set up by selecting in priority order, row by row and column by column, one of the cells of the array containing a free state bit. IMAGE