Logic performance verification and transition fault detection

摘要

In scan testing of logic parts, this invention pro­vides an inexpensive transition fault test by changing the sequence of application of the A/C and B clocks. In each machine test cycle the B clock is triggered first, and the A/C clock is triggered second. The periodicity of the clocks is not changed for a parti­cular cycle, because in one cycle the B-to-A/C clock­ing that naturally occurs provides a minimum test window TP for performance and transition fault testing. Thus, less sophisticated scan test equipment can now provide both transition fault and stuck fault testing, without an increase in complexity or expense.