ABSTRACTIn scan testing of logic parts, this invention providesan inexpensive transition fault test by changing the sequenceof application of the A/C and B clocks. In each machine testcycle the B clock is triggered first, and the A/C clock istriggered second. The periodicity of the clocks is not changedfor a particular cycle, because in one cycle the B-to-A/Cclocking that naturally occurs provides a minimum test windowTP for performance and transition fault testing. Thus, lesssophisticated scan test equipment can now provide bothtransition fault and stuck fault testing, without an increasein complexity or expense.BU9-87-035
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