INTERFACE BETWEEN POSITIVE ECT LOGIC AND NEGATIVE ECL LOGIC

摘要

The interface circuit includes a positive ECL (emitter coupled logic) output circuit (10) for processing inputted positive ECL signals to output positive ECL signals, with its first power terminal (VEE) receiving a first voltage (GNG), and with its second power terminals (Vcc1,Vcc2) receiving a second voltage (+Vcc). A level shifting interface (26) is connected between the positive ECL output circuit (10) and a negative ECL output circuit (24) through its own capacitor (C). The level shifting interface (26) further includes resistors (R1)(R2) which are connected between the first voltage (GND) and a third voltage (-VEE) in series, and which divide the third voltage to overlappingly supply the divided voltage to the capacitor (C). Further, the interface (26) level-shifts the positive ECL signals to negative ECL signals.