The borderless master slice semiconductor device for freely setting the size of a master chip by forming an independent basec cell structure with matrix shape on the front surface of a wafer comprises first conduction type of independent well regions (20) arranged in a row direction on the front surface of the second conductive semiconductor wafer, a second conductive MOS transistor group (21) arranged in the well regions in a row direction and having current paths and gate terminals, first conductive diffusion regions (22) arranged to both sides of the group (21); second conductive intermediate regions (30) formed betwen the well regions (20), a first MOS transistor group (31) arranged in the intermediate regions (30) in a row direction and having current paths and gate terminals, and second conductive regions (32) arranged to both sides of the group (31).
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