Iterative multiplier circuit for 5211-coded decimal numbers - halts multiplication after processing of final multiplier digit

摘要

The multiplicand is clocked into a shift register (1), and iteratively added into an intermediate result shift register (2), via a full decade adder circuit (3) with carry buffer (4). Completed result digits are gated into the result register (6) by a gating circuit (5). A control unit is provided with pref. two impulse counters which stop the multiplication process as soon as etc. last multiplier digit has been processed.