Multiplier circuit for 5211-coded decimal arithmetic - uses eight-decade shift register with rotation for result accumulation and additional shift registers for final result

摘要

This circuit uses bit-serial single-direction shift registers (5a,5b) to accumulate results. The eight-digit multiplicand and multiplicator are loaded into decade shift-registers (A,B). Digits are fed to the decade multiplier (1) and decade adders (2,3). Carry propagation is performed by the carry-adder circuits (4). For each multiplicator digit, the multiplicand register (A) and the intermediate result register (5b) perform a full 8-digit rotation, and the least significant result digit is shifted into the final result register (5a).