Digital adder circuit - has inputs received by stage that effects bit shift prior to processing

摘要

A digital electronic circuit for the addition of two 54321 decimally coded numbers (A,B) generates a result in the same code. The inputs are received by a circuit that has 5 stages (25) formed from AND gates that allow different bit shifts to be made dependent upon the code combinations. The generate signals are received by an arithmetic unit that has a full adder and logic circuitry to generate a sum output in 54321 code. An alternative version handles numbers in 51111 code. ADVANTAGE - Simplified system for decimally coded numbers.