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DRAM architecture having distributed address decoding and timing control
DRAM architecture having distributed address decoding and timing control
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机译:具有分布式地址解码和时序控制的DRAM体系结构
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摘要
A DRAM has both a distributed row address decode and a distributed timing control to generate required timing signals. A level of decoding is implemented within each of local row decoders to generate critical timing signals for each of a plurality of DRAM bit cell arrays. Word line signals from an output of each of the local row decoders are interleaved. The interleaved word line signals permit a high density DRAM semiconductor manufacturing process to utilize a differing pitch for each of a plurality of levels of interconnect. A first level of interconnect has a pitch which is significantly smaller than the pitch of a second interconnect level positioned above the first level of interconnect.
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