首页> 外国专利> BURIED GATE TYPE STATIC INDUCTION THYRISTOR WITH SILICON THIN FILM LAYER BALLAST RESISTOR

BURIED GATE TYPE STATIC INDUCTION THYRISTOR WITH SILICON THIN FILM LAYER BALLAST RESISTOR

机译:硅薄膜薄膜压载电阻的埋入式栅型静态感应晶闸管

摘要

PURPOSE: To provide a buried gate type static induction thyristor in which a silicon thin film layer ballast resistor is disposed on each cathode region in addition to an inner ballast resistor. ;CONSTITUTION: A basic structure of an element having a ballast resistor for so suppressing an increase in current concentration for each unit cell as not to satisfy turn-on conditions even if current concentration occurs in the cell, and miniaturized in size near a channel width partly directly on a center line of a gate layer 8 as a pair with the layer 8 to selectively dispose an n+ type layer 4. Further, a silicon thin film layer 9' is interposed in contact with a predetermined position of the n+ type layer to a cathode electrode 9. The direction of the current passing through the channel is altered to a lateral direction, a relatively long current passage to the layer 4 is formed, effectively operated as a ballast resistor, the resistance value of the silicon thin layer ballast resistor can be set to a desired value, and a controllable ON-current resistance can be improved about twice as large as a conventional element.;COPYRIGHT: (C)1993,JPO&Japio
机译:目的:提供一种埋栅型静电感应晶闸管,其中,除了内部镇流电阻器之外,还在每个阴极区域上还设置了硅薄膜层镇流电阻器。 ;组成:具有镇流电阻的元件的基本结构,用于即使每个单元中发生电流集中,也抑制每个单元电池的电流浓度增加,从而不满足导通条件,并且在通道宽度附近将其尺寸最小化部分地直接在栅极层8的中心线上与该层8成对,以选择性地设置n + 型层4。此外,硅薄膜层9'插入与之接触。 n + 型层相对于阴极电极9的预定位置。流过沟道的电流方向改变为横向,有效地形成了到层4的较长的电流通道用作镇流电阻器时,可以将硅薄层镇流电阻器的电阻值设置为所需值,并且可控的导通电流电阻可以提高到传统元件的两倍左右。; COPYRIGHT:(C)1993 ,JPO&Japio

著录项

  • 公开/公告号JPH0563185A

    专利类型

  • 公开/公告日1993-03-12

    原文格式PDF

  • 申请/专利权人 TOYO ELECTRIC MFG CO LTD;

    申请/专利号JP19910197025

  • 发明设计人 MURAOKA KIMIHIRO;

    申请日1991-07-11

  • 分类号H01L29/74;

  • 国家 JP

  • 入库时间 2022-08-22 05:17:12

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