Dynamically programmable logic network with NOR-NOR structure, implemented in CMOS technology

摘要

The block circuit which, during the pre-load or pre-unload, inhibits passage of data from the AND plane to the OR plane of a dynamically programmable logic network with NOR-NOR structure, implemented in CMOS technology, comprising a plurality of sections, each of which includes a logical NAND gate with CMOS transistors, which output is connected to a corresponding input of the OR plane toward a singer logic inverter.