Dynamic programmable logic arrays with NOR-NOR structure implemented in C-MOS technology

摘要

The blocking circuits which, during precharge, inhibit the data passage to the AND and OR planes (PA, PO) of a dynamic programmable logic array with NOR-NOR structure, implemented in C-MOS technology, comprise a pair of transistors (MT9, MT10,...; MT22,MT21;...) with complementary channel doping, the first of which controls the signal passage to the AND or the OR plane, respectively, and the second inhi­bits the gates of the respective plane during precharge.