Methodology for Characterization of NOR-NOR Programmable Logic Array

摘要

Programmable Logic Arrays are popular implementations for "multi-input" 2-level "multi-output" functions. PLAs are advantageous for designers especially in GHz technology with deep sub-micron sizing. The regular structures of PLAs are attractive to VLSI designers because they require a small number of separate cell designs. PLAs allow "ease of testing". The biggest advantage is that the entire design flow in the PLA generation can be automated. The main focus of the paper is to establish a quick design verification methodology for PLAs. We choose dynamic PLAs which have an advantage of higher frequency of operation, lesser power consumption and easier predictability of area. The methodology involves generation of spice decks dynamically using Perl code and simulating the PLA's pre-layout net-list in H-Spice. In the post-layout stage layouts are dynamically generated using SKILL programming in Virtuoso and simulating post-layout net-list in H-Spice. Various characterization experiments are done on PLA using this methodology.