A design method for the automatic implementation of data-flow partitions in asic's

摘要

A design method for the automatic implementation of data-flow partitions in integrated circuit chips, typically ASIC's, which takes advantage of the bit-stack features to reach better density and performance. The method is structured from the logical design to the physical design. The logical design of the chip comprises the following main steps :a logic entry step (S1) to capture with a high level language the design of the chip making use of logical macrofunction library to describe data-flow and control logic partitions in a high level logic (D1); and,a structure extraction step (S3) to perform the expansion of the high level logic (D1) in a book level logic (D5) and to generate the hierarchy description (D6), the sorted netlist (D7), and R/C estimates (D8);;The physical design of the chip comprises the following main steps :power assignment (S7), timing analysis (S8), floor planning (S9), placement (S10) and wiring (S11) steps that make use of the data generated during the previous steps to ensure an optimal placement and wiring of the books; and,a mask data generation step (S13) that generates data (D14), from which mask patterns can be produced onto the integrated circuit chips.