Pattern recognition circuit for digital transmission path testing - uses standard logic modules to verify test pattern comprising repetitive sequence of two different bytes

摘要

The pattern recognition circuit is used for a repetitive bit pattern, sequence applied to one or more channels of a digital transmission path and uses standard programmable logic modules. A clock signal correlated with the tested channel(s) is applied to a clock input, with a number of parallel data inputs receiving the bits of the bit pattern after series/parallel conversion and coupled via a set of inverters (EP,EQ) to a pair of AND gates (71,72). The latter are coupled to an OR gate (73), in turn coupled to an error flip-flop (35), a second OR gate (79) coupled to the data input of a synchronisation flip-flop (34). USE - For on-line testing of digital exchange.