A method for testing the reliability of an integrated circuit chips and a circuit for carrying out this test.

摘要

Disclosed herein is a method and circuit useful in the testing of integrated circuit chips (10). On-chip test circuitry (12) is provided at a selected location on an IC chip (10) and energized while the chips (10) are still mounted on a lead frame member (48), wound on reels (68) and heated in an oven (70). Advantageously, the continuous lead frame member (62) may be a tape automated bond (TAB bond) flexible circuit (48) which is adapted for gang bonding to a large plurality of ICs before being wound on reels (68). In a preferred test circuit embodiment, the conductive on-off state of digital address circuitry (12) is controlled by applying a test signal potential to an input test pad (18) and through a fuse (20) to a common test circuit junction (21). This junction (21) is in turn connected between a transistor (38) and diode (36) in a series control network which is operative to control the conductive state cf the address circuitry (12). This network enables the input test pad (18) to be used as both a test input connection and a ground connection for the IC test circuit(12).