首页> 外国专利> Semiconductor package e.g. lead-on-chip, small outline J-lead type - has chip with several solder points which are soldered to numerous inner lines of conductor frame

Semiconductor package e.g. lead-on-chip, small outline J-lead type - has chip with several solder points which are soldered to numerous inner lines of conductor frame

机译:半导体封装芯片上引线,小轮廓J引线型-带有多个焊点的芯片,这些焊点被焊接到导体框架的许多内线上

摘要

The semiconductor chip in the package has a number of soldering points on its plastics lines. There are numerous inner lines of a conductive frame, soldered to the points, which may be of Pb-Sn alloy etc. whose melting temp. is higher than that of the epoxy hardening temp. Each soldering point is typically spherical, with the plastics lines of the chip set along a longitudinal line. Alternatively they are arranged along two such lines. They may be also of zigzag shape. In the mfg., polyimide films are formed on the semiconductor chip surface, and the soldering points are formed on each plastics line. USE/ADVANTAGE - Also for MSP, QFP-type packages, e.g. for memory integrated circuit chips, with improved design reduced package thickness, without using wire bonding process.
机译:封装中的半导体芯片在其塑料线上具有许多焊接点。导电框架的许多内线焊接到这些点上,这些内线可能是熔化温度为Pb-Sn合金等。高于环氧硬化温度。每个焊接点通常是球形的,芯片的塑料线沿纵向线设置。或者,它们沿着两条这样的线排列。它们也可以是之字形。在制造中,在半导体芯片表面上形成聚酰亚胺膜,并且在每条塑料线上形成焊接点。使用/优势-同样适用于MSP,QFP类型的包装,例如用于存储器集成电路芯片,改进的设计减小了封装厚度,而无需使用引线键合工艺。

著录项

  • 公开/公告号DE4215471A1

    专利类型

  • 公开/公告日1992-11-12

    原文格式PDF

  • 申请/专利权人 GOLDSTAR ELECTRON CO. LTD. CHEONGJU KR;

    申请/专利号DE19924215471

  • 发明设计人 CHA GI BON KYUNGKI KR;

    申请日1992-05-11

  • 分类号H01L23/50;H01L23/28;

  • 国家 DE

  • 入库时间 2022-08-22 05:01:18

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