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Bipolar-CMOS integrated circuit having a structure suitable for high integration

机译:具有适合于高集成度的结构的双极CMOS集成电路

摘要

Herein disclosed is a bipolar-CMOS semiconductor circuit having a semiconductor substrate, an N.sup.- epitaxial layer formed on the semiconductor substrate, an N well formed in the N.sup.- epitaxial layer, a P well formed in the N.sup.- epitaxial layer, a power supply terminal to which the positive potential is to be supplied, a ground potential terminal, an input terminal, an output terminal, an NPN bipolar transistor formed in the N.sup.- epitaxial layer, the NPN bipolar transistor having the N.sup.- epitaxial layer as the collector thereof and having an emitter connected to the output terminal, a P-channel type MOS transistor formed in the N well and being connected between the power supply terminal and the base of the NPN bipolar transistor, the gate of the P-channel type MOS transistor being connected to the input terminal, and both the N well for the P-channel type MOS transistor and the N.sup.- epitaxial layer as the collector of the NPN bipolar transistor being connected to the power supply terminal, and an N-channel type MOS transistor formed in the P well and being connected between the output terminal and the ground potential terminal, the gate of the N-channel type MOS transistor being connected to the input terminal.
机译:本文公开了一种双极CMOS半导体电路,其具有半导体衬底,形成在半导体衬底上的N-外延层,形成在N-外延层中的N阱,形成在N中的P阱。上-外延层,要向其提供正电位的电源端子,地电位端子,输入端子,输出端子,在N-外延层中形成的NPN双极晶体管,NPN具有N-外延层作为其集电极并具有连接到输出端的发射极的双极晶体管,在N阱中形成并连接在电源端和基极之间的P沟道型MOS晶体管。 NPN双极型晶体管,P沟道型MOS晶体管的栅极连接到输入端子,P沟道型MOS晶体管的N阱和NPN双极的集电极作为外延层晶体管连接到电源端子,和形成在P阱中并连接在输出端子和接地电位端子之间的N沟道型MOS晶体管,N沟道型MOS晶体管的栅极连接到输入端子。

著录项

  • 公开/公告号US5168341A

    专利类型

  • 公开/公告日1992-12-01

    原文格式PDF

  • 申请/专利权人 NEC CORPORATION;

    申请/专利号US19910675665

  • 发明设计人 KOUICHI KUMAGAI;KENJI YOSHIDA;

    申请日1991-03-27

  • 分类号H01L27/02;

  • 国家 US

  • 入库时间 2022-08-22 04:59:07

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